CHDL1: Implementing a simplified version of the CompactHDL hardware description language

Florin-Marian Birleanu


A few years ago an extremely compact hardware description language was proposed. This paper presents the implementation of a subset of that language. For this implementation the JavaCC code generator was used and the resulted application runs on any operating system having Java installed. The application receives the description of the desired logic circuit in the new language and generates the VHDL source files as well as the user constraints file required for implementing the circuit in a FPGA board. The implemented subset of the language allows the user to easily describe any combinatorial logic circuit based on NOT, AND and OR gates. It also makes it very easy to create and use components and to specify pin constraints.

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