An Efficient (Low Resources) Modular Hardware Implementation of the AES Algorithm

Paul BURCIU

Abstract


Modularity is one of today’s key factors concerning either software and hardware implementations. Cryptography does not make exception to this tendency, thus the main objective of this paper being author’s approach regarding a modular hardware implementation of the AES symmetric crypto-system, using a Finite State Machine with Datapath (FSMD) structure. The main idea of this implementation is to modularly integrate every cryptographic operation of AES, such as bytes’ substitution or shifting, column multiplication on Galois Field, or adding round keys, as a first level of modularity, and then, every macro-operation of AES, such as the encryption/decryption round or the key expansion, as a second level of modularity. This paper offers an efficient (low resources) modular hardware implementation of an AES crypto-system, studying the implication of different design solutions susceptible to be used, pointing advantages and disadvantages of such an approach.

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References


FIPS, PUB 197, “Announcing the Advanced Encryption Standard (AES)”, U.S.A., 2001.

Francisco Rodriguez-Henriquez, N.A. Saqib, A. Diaz-Perez, Cetin Kaya Koc, “Cryptographic Algorithms on Reconfigurable Hardware”, Springer Science+Business Media LLC, New York, U.S.A., 2006.

Xilinx ISE 14.7 programming platform (shareware version).

Pong P. Chu, “FPGA prototyping by VHDL examples”, John Wiley & Sons, Inc., Hoboken, New Jersey, U.S.A., 2008.


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